49. Vhdl-модель операционного автомата

Листинг 6.1 – VHDL-модель операционного модуля (автомата)

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.std_logic_unsigned.all;

entity OA is

port(

Done, y1, y2, y3, y4, y5, y6, CLK: in STD_LOGIC; -- control signals

A : in STD_LOGIC_VECTOR(5 downto 0); -- summand

B : in STD_LOGIC_VECTOR(5 downto 0); -- summand

C : out STD_LOGIC_VECTOR(5 downto 0); -- sum

x1, x2, x3 : out STD_LOGIC; -- informative signals

pp: out STD_LOGIC -- overflow

);

end OA;

--}} End of automatically maintained section

architecture OA of OA is

-- enter your statements here --

signal RG:STD_LOGIC_VECTOR(5 downto 0); -- - register

signal SM:STD_LOGIC_VECTOR(5 downto 0); -- - register-adder

begin

process (CLK, y1, y2, y3, y4, y5, y6)

begin

if (CLK'event and CLK='1')then

If (y1 = '1' and y2 = '1') then

RG <=B;

SM <=A;

elsif (y3 = '1')then

SM <=SM(5 downto 4) & ((not SM(3 downto 0))+1);

elsif (y4 = '1')then

SM <= SM + (RG(5 downto 4) & ((not RG(3 downto 0))+1));

elsif (y5 = '1')then

SM <= SM + RG;

elsif (y6 = '1')then

pp <= '1';

else pp <= '0';

end if;

end if;

end process;

C <= SM when Done = '1' else (others =>'0');

x1<= '1'when SM(5 downto 4)="11" else '0';

x2<= '1'when RG(5 downto 4)="11" else '0';

x3<= '1'when SM(5 downto 4)="01" or SM(5 downto 4)="10" else '0';

end OA;

На рис. 6.4 Приведены временные диаграммы работы операционного автомата.

Рисунок 6.4 – Временные диаграммы работы операционного автомата